rev 2.0 ?2012 advanced linear devices, inc. 415 tasman drive, sunnyvale, ca 94089-1706 tel: (408) 747-1155 fax: (408) 747-1286 www.aldinc.com dual p-channel matched mosfet pair ald1102a/ald1102b ald1102 a dvanced l inear d evices, i nc. general description the ald1102 is a monolithic dual p-channel matched transistor pair intended for a broad range of analog applications. these enhancement- mode transistors are manufactured with advanced linear devices' en- hanced acmos silicon gate cmos process. the ald1102 offers high input impedance and negative current tempera- ture coefficient. the transistor pair is matched for minimum offset voltage and differential thermal response, and it is designed for switching and amplifying applications in +2v to +12v systems where low input bias current, low input capacitance and fast switching speed are desired. since these are mosfet devices, they feature very large (almost infinite) current gain in a low frequency, or near dc, operating environment. when used with an ald1101, a dual cmos analog switch can be constructed. in addition, the ald1102 is intended as a building block for differential amplifier input stages, transmission gates, and multiplexer applications. the ald1102 is suitable for use in precision applications which require very high current gain, beta, such as current mirrors and current sources. the high input impedance and the high dc current gain of the field effect transistors result in extremely low current loss through the control gate. the dc current gain is limited by the gate input leakage current, which is specified at 50pa at room temperature. for example, dc beta of the device at a drain current of 5ma at 25 c is = 5ma/50pa = 100,000,000. applications ? precision current mirrors ? precision current sources ? analog switches ? choppers ? differential amplifier input stage ? voltage comparator ? data converters ? sample and hold ? analog inverter features ? low threshold voltage of 0.7v ? low input capacitance ? low vos grades -- 2mv, 5mv, 10mv ? high input impedance -- 10 12 w typical ? low input and output leakage currents ? negative current (i ds ) temperature coefficient ? enhancement-mode (normally off) ? dc current gain 10 9 ? rohs compliant operating temperature range 0 c to +70 c0 c to +70 c -55 c to +125 c 8-pin 8-pin 8-pin small outline plastic dip cerdip package (soic) package package ald1102asal ALD1102APAL ald1102bsal ald1102bpal ald1102sal ald1102pal ald1102da * contact factory for leaded (non-rohs) or high temperature versions. ordering information (l suffix denotes lead-free (rohs)) block diagram pin configuration 1 2 3 4 8 7 6 5 source 1 gate 1 drain 1 nc substrate source 2 gate 2 drain 2 top view sal, pal, da packages * nc pin is internally connected. do not connect externally. source 1 (1) substrate (8) source 2 (7) gate 2 (6) drain 1 (3) gate 1 (2) drain 2 (5)
ald1102a/ald1102b/ald1102 advanced linear devices 2 of 6 drain-source voltage, v ds -10.6v gate-source voltage, v gs -10.6v power dissipation 500mw operating temperature range sal, palpackages 0 c to +70 c da package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment. absolute maximum ratings gate threshold voltage v t -0.4 -0.7 -1.2 -0.4 -0.7 -1.2 -0.4 -0.7 -1.2 v i ds = -10 m a v gs = v ds offset voltage v os 2 5 10 mv i ds = -100 m a v gs = v ds v gs1 - v gs2 gate threshold tc vt -1.3 -1.3 -1.3 mv/ c temperature drift on drain current i ds (on) -8 -16 -8 -16 -8 -16 ma v gs = v ds = -5v transconductance g fs 2 4 2 4 2 4 mmho v ds = -5v i ds = -10ma mismatch d g fs 0.5 0.5 0.5 % output g os 500 500 500 m mho v ds = -5v i ds = -10ma conductance drain source r ds(on) 180 270 180 270 180 270 w v ds = -0.1v v gs = -5v on resistance drain source on resistance d r ds(on) 0.5 0.5 0.5 % v ds = -0.1v v gs = -5v mismatch drain source breakdown bv dss -12 -12 -12 v i ds = -10 m a v gs =0v voltage off drain current i ds(off) 0.1 4 0.1 4 0.1 4 na v ds =-12v v gs = 0v 444 m at a = 125 c gate leakage i gss 150 150 1 50pa v ds =0v v gs =-12v current 10 10 10 na t a = 125 c input c iss 6 10 6 10 6 10 pf capacitance operating electrical characteristics t a = 25 c unless otherwise specified 1102a 1102b 1102 test parameter symbol min typ max min typ max min typ max unit conditions
ald1102a/ald1102b/ald1102 advanced linear devices 3 of 6 typical performance characteristics output characteristics drain - source voltage (v) drain - source current (ma) -80 -60 -40 -20 0 v bs = 0v t a = 25 c -10v -8v -6v -4v -2v 0-8 -2 -6 -4 -10 -12 v gs = -12v low voltage output characteristics drain -source voltage (mv) drain-source current (ma) -320 -160 0 160 320 -4 4 2 0 -2 -4v v gs = -12v -6v v bs = 0v t a = 25 c -2v -12 forward transconductance vs. drain - source voltage drain - source voltage (v) 0-8 -2 -6 -4 -10 forward transconductance ( mho) 10000 5000 2000 1000 500 200 100 v bs = 0v f = 1khz i ds = -5ma t a = +125 c t a = +25 c i ds = -1ma transfer characteristic with substrate bias gate - source voltage (v) 0 -0.8 -1.6 -2.4 -3.2 -4.0 -20 -15 -10 -5 0 drain-source current ( a) v bs = 0v 4v 6v 8v 10v 12v v gs = v ds t a = 25 c 2v gate - source voltage (v) r ds (on) vs. gate - source voltage drain - source on resistance ( ) 10000 1000 100 10 -2 0 -4 -6 -8 -10 -12 v ds = 0.4v v bs = 0v t a = +125 c t a = +25 c off drain - current vs. temperature temperature ( c) off - drain source current (a) -50 -25 +25 +50 +75 +125 +100 0 -10 x 10 -6 v ds = -12v v gs = v bs = 0v -10 x 10 -12 -10 x 10 -9
ald1102a/ald1102b/ald1102 advanced linear devices 4 of 6 8 pin plastic soic package soic-8 package drawing millimeters inches min max min max dim a a 1 b c d-8 e e h l s 1.75 0.25 0.45 0.25 5.00 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.185 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.196 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 4.69 3.50 5.70 0.60 0 0.25 l c h s (45 ) e a a 1 b d s (45 ) e
ald1102a/ald1102b/ald1102 advanced linear devices 5 of 6 8 pin plastic dip package pdip-8 package drawing b 1 s b e e 1 d e a 2 a 1 a l c e 1 millimeters inches min max min max dim a a 1 a 2 b b 1 c d-8 e e 1 e e 1 l s-8 3.81 0.38 1.27 0.89 0.38 0.20 9.40 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 11.68 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.370 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.460 0.280 0.325 0.110 0.310 0.150 0.080 15
ald1102a/ald1102b/ald1102 advanced linear devices 6 of 6 8 pin cerdip package cerdip-8 package drawing a a 1 b b 1 c d-8 e e 1 e e 1 l l 1 l 2 s 3.55 1.27 0.97 0.36 0.20 -- 5.59 7.73 3.81 3.18 0.38 -- 0 5.08 2.16 1.65 0.58 0.38 10.29 7.87 8.26 5.08 -- 1.78 2.49 15 millimeters inches min max min max dim 0.140 0.050 0.038 0.014 0.008 -- 0.220 0.290 0.150 0.125 0.015 -- 0 0.200 0.085 0.065 0.023 0.015 0.405 0.310 0.325 0.200 -- 0.070 0.098 15 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc e e 1 c e 1 s b l d b 1 e a l 2 a 1 l 1
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